Thin film deposition techniques are used in a variety of applications. One field where such techniques take on particular importance is in the manufacturing of microfeatures, which employ a thin coating on a workpiece that closely conforms to the surface topography. For example, such techniques may be used to deposit successive thin layers of capacitors used in DRAM memory cells. One thin film deposition technique widely used in the microelectronics industry is chemical vapor deposition (CVD). In a CVD system, one or more precursors that are capable of reacting to form a solid thin film are mixed in a gas or vapor state and this precursor mixture is presented to the surface of the workpiece. The surface of the workpiece catalyzes the reaction between the precursors to form a solid thin film on the workpiece surface.
A common way to catalyze the reaction at the surface of the workpiece is to heat the workpiece to a temperature that causes the reaction. For some CVD reactions, the deposition rate and the quality of the deposited layer are optimized in a relatively narrow band of temperatures. In addition, many semiconductor workpieces have a “heat budget” that reflects the cumulative adverse effects of elevated temperatures on the semiconductor substrate. Optimizing the deposition process while minimizing the impact on the heat budget requires relatively precise control over the temperature in the CVD process.
Although current temperature management techniques have proven acceptable in the deposition of common materials, e.g., silicon nitride and polycrystalline silicon (also referred to as “polysilicon”), newer microelectronic component designs are increasingly incorporating other materials in their designs. Some of these materials present significant manufacturing challenges. For example, some microfeature workpiece manufacturing processes require deposition of materials that are more reflective of radiant heat than the more conventional silicon nitride and polysilicon films. Batch CVD reactors used in manufacturing microelectronic components commonly heat the microfeature workpieces during the CVD process via radiant heat. For example, U.S. Patent Application Publication 2001/0029892, the entirety of which is incorporated herein by reference, illustrates a batch plasma enhanced CVD system in which a series of radiant heat panels are arranged around the outside of a deposition chamber. When depositing radiant heat-reflective materials on workpieces in such a CVD system, some of the material also will be deposited on an inner surface of the deposition chamber walls. This reflective layer reflects the heat that is intended to heat the workpieces, thereby reducing efficiency. Even more problematic, the reflective build-up on the deposition chamber walls causes a thermal lag between the delivery of power to the radiant heat source and an increase in the temperature in the chamber.
As illustrated in International Publication No. WO 02/073660, the entirety of which is incorporated herein by reference, some CVD reactors employ one or more inner thermocouples within the deposition chamber and one or more outer thermocouples outside the deposition chamber. The outer thermocouples tend to bear a more direct relationship to the energy being delivered by the heat source, and the inner thermocouples, in contrast, tend to more accurately indicate the temperature in the chamber. As a consequence, the outer thermocouples are usually used to control the heat source when ramping up the temperature to the intended deposition temperature. Once the workpieces are at the deposition temperature, control of the heat source is guided by the inner thermocouples to maintain the deposition temperature within an acceptable range during the deposition process. When depositing conventional materials such as polysilicon, the temperature reading of the inner thermocouples may lag the reading of the outer thermocouples somewhat, but this thermal lag tends to be fairly predictable and can be accounted for empirically in the control system.
If a heat-reflective material is being deposited, however, deposition of the material on the chamber walls with successive workpieces reduces the percentage of the heat output actually reaching the interior of the deposition chamber. In addition, the heat reflected by the deposited material is directed back at the outer thermocouples and the heating elements, further increasing the thermal lag over time. One temperature control problem attributable to this increased thermal lag is illustrated schematically in FIG. 1. In FIG. 1, the temperature TO measured by one of the outer thermocouples increases significantly more quickly than the temperature TI measured by one of the inner thermocouples. As suggested in this schematic drawing, the temperature TO measured by the outer thermocouple may reach or exceed the intended deposition temperature TD before the temperature TI measured by the inner thermocouples begins to significantly increase. Delivering more power to the heaters to more rapidly heat the interior of the deposition chamber can heat the outer thermocouple and the radiant heat source to a maximum safe operating temperature TMAX, causing the CVD system to abort the heating process to protect the heat source from damage.
Even if the thermal lag is managed effectively when ramping up the temperature in the deposition chamber, the reflective layer on the wall of the deposition chamber makes it more difficult to maintain the temperature in the chamber at a constant level over time. As suggested in FIG. 2, the thermal lag induced by the increased reflectance can lead to significant oscillations in the temperature in the deposition chamber. When one of the inner thermocouples registers a temperature TI that falls below the targeted deposition temperature, power may be delivered to the heat source to bring the temperature back up. By the time the inner thermocouple reaches the target temperature again, the heat source has already delivered too much energy and the temperature in the chamber overshoots the target. To compensate, the heat source power is reduced to a level below that necessary to maintain the targeted temperature, which can again cause the temperature TI measured by the inner thermocouple to drop below the targeted temperature, starting the cycle again. This cycle can lead to temperature oscillations with increasing amplitude over time. As the process continues, the amplitude of the oscillations may equal or exceed the width of an acceptable deposition temperature range TX, leading to suboptimal material deposition conditions.
One way to address these difficulties is to clean the deposition chamber to remove built-up material deposited on the walls of the chamber. This typically involves a plasma dry clean process and a subsequent seasoning of the chamber walls. Particularly for batch CVD systems, this cleaning process can be fairly time-consuming. This downtime significantly reduces the throughput of the CVD system.